The present invention relates to a frequency synthesizer circuit used for mobile transmission systems, and more particularly to an improved frequency synthesizer which suppresses frequency instability due to intermittent operation of a phase-locked loop circuit.
A phase-locked loop (hereinafter "PLL") type frequency synthesizer is widely used as a stable frequency generator for providing various frequencies at predetermined frequency intervals. For example, PLLs are used as local oscillators in mobile communication systems. These systems require that the receiving frequency be shifted as the receiver is travelling so in order that an idle frequency channel alotted to the area can be found.
In such mobile systems, it is important to minimize power consumption. In frequency synthesizers, the PLL circuit consumes a large percentage of the frequency synthesizer power consumption. This is because the PLL circuit comprises bipolar transistor elements which consume a relatively high amount of power, especially at high frequencies. Other circuits in a mobile communication system can be constructed using field effect transistor elements which consume a relatively low amount of power. Therefore, in order to reduce power consumption in a mobile communication system, the PLL circuit is generally only operated intermittently. In a mobile communication system, the frequency synthesizer must to be very stable, because the frequency allocations for mobile communications systems are very close to each other. Therefore, a very small fluctuation in the frequency generated by a frequency synthesizer causes the system to malfunction.
In order to clarify the problem caused by frequency fluctuations in a PLL frequency synthesizer and to illustrate the advantages of the present invention, the structure and operation of a frequency synthesizer is briefly described.
Frequency synthesizers generally utilize a PLL to generate the required frequencies. PLL circuits normally include a voltage controlled oscillator (VCO), a reference oscillator, and a phase detector which compares the output of the VCO with a reference frequency. Normally, a prescaling frequency counter and one or more programmable or switchable frequency dividers are also included with the PLL so that the loop can be locked to various multiples of the reference frequency.
The prescaling counter (usually called a prescaler) counts down the frequency output by the VCO, which serves as the output frequency of the synthesizer and usually a very high frequency, to a lower frequency at which low speed integrated circuit devices are capable of operating.
If the frequency of the reference oscillator is f.sub.r, the count down ratio of the prescaler and of the programmable frequency divider are 1/P and 1/N respectively, the output frequency f.sub.out becomes: EQU f.sub.out =N.multidot.P.multidot.f.sub.r
Accordingly, the output frequency is an integral multiple of the reference frequency f.sub.r which is stabilized via a crystal oscillator. It is therefore possible to provide a stable frequency signal at any one of a plurality of frequencies separated by the reference frequency f.sub.r, without the need of a crystal oscillator for each frequency. The above described method is generally called a prescaling method. Modifications of the prescaling method are disclosed in, for example, Vadio Manassewitsch, "Frequency Synthesizers Theory and Design," John Wiley & Sons, Inc., 1976. One such modification is the pulse swallow method. Because such modifications are known to those skilled in the art, a detailed explanation of the modifications is omitted.
Basic frequency synthesizers are described in, for example: U.S. Pat. No. 4,521,918 issued on June 4, 1985 to R. F. Challen, which discloses a fundamental frequency synthesizer; and Japanese Laid Open Patents Provisional No. 58-159029 by Nishiki et al., No. 58-66422 by Ohba et al. and No. 58-66423 by Fujita et al. Each of these documents refers to minimizing power consumption of a PLL circuit by operating it intermittently. The PLL circuit is operated intermittently because a large amount of frequency synthesizer power is consumed by the bipolar devices included in the PLL circuit, especially in the prescaling circuit which operates at a very high frequency.
However, the inventors have determined that when a PLL circuit is operated intermittently there is a short period of time during which the output frequency of the frequency synthesizer is unstable. This period of time corresponds to the time for the frequency counter to start after the PLL circuit is switched. Because of this frequency instability, many mobile communication systems must include means to prevent malfunctions due to the frequency instability.